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Design of hybrid memory using ECC, EDC, & BIST using Verilog and verification using system Verilog.
Random Access Memory (RAM) system has been designed and functionally verified using Verilog HDL and SystemVerilog-based verification environment. The RAM module incorporates Error Correction Code (ECC) and Built-In Self-Test (BIST) mechanisms to enhance data integrity and reliability against transient and permanent faults, which are critical in safety-critical and high-reliability systems.The ECC encoder implements a Hamming SEC-DED (Single Error Correction) scheme by generating 5 parity bits for every 16-bit data, resulting in a 21- bit encoded output. During read operations, the ECC decoder computes the syndrome to detect and correct single-bit errors and flag double-bit errors. The BIST controller automates the test process by writing known patterns into memory, reading them back, and comparing the values to detect permanent faults without external test equipment. The top-level module integrates the RAM, ECC encoder/decoder, and BIST controller. It supports normal operation mode and self-test mode, making the system capable of runtime error detection and correction. The entire design is validated using a SystemVerilog testbench to ensure functional correctness under various scenarios, including fault injection and random stimuli. Simulation results confirm the system's ability to correct single-bit errors, detect double-bit errors, and identify memory faults, demonstrating its effectiveness and reliability in fault-prone environments
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