Arshiya Farheen, Raja Kumar Rudrarapu 03 07 MultiplyAccumulate MAC integrates an arithmetic framework for highspeed and energyefficient VLSI computation Recent studies indicate that MAC operations contribute nearly 6075 of total execution time and over 65 of dynamic power consumption in modern DSP and AI accelerators while parallel MAC architectures can improve throughput by more than 3 with up to 40 energy reduction when optimized arithmetic units are employed Traditional MAC designs rely on conventional multipliers and carrypropagationbased adders leading to long critical paths excessive switching activity poor scalability and increased areapower overhead when extended to parallel multiMAC configurations Moreover replicating complete arithmetic blocks with independent control logic further aggravates energy inefficiency and design complexity in largescale systems To address these limitations the proposed architecture introduces a Unified GroupDecomposed Multiplier UGDM that performs hierarchical operand decomposition and parallel partialproduct generation significantly shortening the multiplication critical path and reducing unnecessary transitions In addition a Predictive SkipMerge Adder PSMA is employed for accumulation which combines speculative carry prediction with selective skipmerge paths to accelerate summation without full carry propagation Multiple MAC units are instantiated in parallel using this single novel multiplieradder pair and governed by a centralized shared control logic enabling synchronized operation reduced hardware redundancy and scalable throughput The entire framework is realized through automated Verilog generation ensuring flexibility across operand widths while achieving enhanced speed lower energy consumption and improved suitability for nextgeneration DSP systems Copyright (c) Journal of Science Engineering Technology and Management Science. All rights reserved 2026