Article
Variational Quantum Circuit Regressors for Joint Optimization of Transistor Scaling and Die Footprint in Advanced IC Manufacturing
In advanced IC manufacturing, yield losses contribute to nearly 20–30% of total fabrication cost, with variations in die size and transistor scaling responsible for more than 60% of yield degradation, while modern fabs generate terabytes of process data per production cycle, making efficient prediction essential. Existing manual and traditional yield prediction approaches rely on low-level statistical analysis and expert-driven rule formulation, resulting in high time consumption, poor scalability, limited ability to model non-linear interactions, and reduced reliability at advanced technology nodes. To address these limitations, this work proposes a Quantum Neural Network–based yield prediction framework for accurate estimation of die size and transistor scaling, where the Integrated Chip (IC) manufacturing dataset is first subjected to comprehensive data preprocessing including normalization, noise reduction, and missing-value handling, followed by Exploratory Data Analysis (EDA) to identify key statistical trends and process correlations. For performance comparison, existing models such as the Restricted Boltzmann Machine (RBM) Regressor, Gradient Boosting Regressor (GBR), and Extreme Gradient Boosting (XGB) Regressor are implemented to evaluate classical learning capabilities. The proposed system integrates a Variational Quantum Neural Network (VQNN) for advanced quantum feature extraction, leveraging parameterized quantum circuits to capture highdimensional, non-linear, and entanglement-based relationships among manufacturing parameters, which are difficult to model using classical methods. These quantum-enhanced features are then processed using an Ensemble Oblique Trees (EOT) regressor to achieve robust and highly accurate yield prediction, significantly improving prediction accuracy, adaptability, and computational efficiency, thereby enabling early-stage yield optimization and cost reduction in next-generation IC manufacturing
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