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EFFICIENT VLSI ARCHITECTURE FOR OTFS MODULATION WITH ZERO-FORCING EQUALIZATION
Orthogonal Time Frequency Space (OTFS) modulation is a promising technique known for its robustness in time-varying channels, making it well-suited for high-mobility communication environments. This project focuses on the design and hardware implementation of a low-complexity Zero Forcing (ZF) equalizer for a Single-Input Single-Output (SISO) OTFS system. To reduce computational complexity and hardware overhead, we propose a Very Large Scale Integration (VLSI) architecture that incorporates parallel processing and resource optimization techniques. A key feature of the design is the use of a back-to-back Fast Fourier Transform (FFT) and Inverse FFT (IFFT) structure, which simplifies matrix inversion operations and allows for efficient updates without significantly degrading performance. The architecture is carefully crafted to support real-time processing while satisfying area and latency requirements. Through extensive simulations and evaluations, we study the trade-offs between reduced complexity and equalization performance. Performance metrics such as Bit Error Rate (BER), latency, and hardware area are used to evaluate the design. Synthesis results on a Xilinx 7vx485tffg1157-1 FPGA demonstrate the effectiveness of the proposed architecture, achieving a latency of 440 ns at a 100 MHz clock frequency, utilizing 249,843 Look-Up Tables (LUTs) and 74,611 Flip-Flops (FFs).
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