Article
ENERGY EFFICIENT SECURE MEMORY ELEMENTS IN DIGITAL DEVICES
Low complexity turbo-like codes based on simple two-state trellis or simple graph structure results in encoding with low complexity. Out of this Convolution encoder and turbo codes are widely used due to the excellent error control performance. The most popular communications encoding algorithm, the iterative decoding requires an exponential increase in hardware complexity to achieve greater encode accuracy. This project focuses on the realization of turbo encoder and decoder using Log-Map based Iterative decoding technique.The turbo codes are designed with the help of Recursive Systematic Convolutional and are separated by inter leaver, which (component used to rearrange the bit sequence) plays a vital role in the encoding process. This paper provides the design of a Turbo Encoder, which is parallel concatenation of Recursive Systematic Convolutional (RSC) encoders and inter leaver to reduce delay. The Turbo Encoder is designed by Verilog-HDL and Synthesized by Xilinx ISE.
Full Text Attachment
