Journal of Science Engineering Technology and Management Science

Multiply–Accumulate (MAC) integrates an arithmetic framework for high-speed and energy-efficient VLSI computation. Recent studies indicate that MAC operations contribute nearly 60–75% of total execution time and over 65% of dynamic power consumption in modern DSP and AI accelerators, while parallel MAC architectures can improve throughput by more than 3× with up to 40% energy reduction when optimized arithmetic units are employed. Traditional MAC designs rely on conventional multipliers and carry-propagation-based adders, leading to long critical paths, excessive switching activity, poor scalability, and increased area–power overhead when extended to parallel multi-MAC configurations. Moreover, replicating complete arithmetic blocks with independent control logic further aggravates energy inefficiency and design complexity in large-scale systems. To address these limitations, the proposed architecture introduces a Unified Group-Decomposed Multiplier (UGDM) that performs hierarchical operand decomposition and parallel partial-product generation, significantly shortening the multiplication critical path and reducing unnecessary transitions. In addition, a Predictive Skip-Merge Adder (PSMA) is employed for accumulation, which combines speculative carry prediction with selective skip–merge paths to accelerate summation without full carry propagation. Multiple MAC units are instantiated in parallel using this single novel multiplier–adder pair and governed by a centralized shared control logic, enabling synchronized operation, reduced hardware redundancy, and scalable throughput. The entire framework is realized through automated Verilog generation, ensuring flexibility across operand widths while achieving enhanced speed, lower energy consumption, and improved suitability for next-generation DSP systems.

Keywords : Multiply–Accumulate (MAC), Unified Group-Decomposed Multiplier (UGDM), Predictive Skip-Merge Adder (PSMA), Digital Signal Processing (DSP), Parallel Arithmetic Architecture, Low-Power VLSI, High-Speed Computing, Hardware Acceleration.

Author : Arshiya Farheen, Raja Kumar Rudrarapu

Title : Unified Group-Decomposed MAC with Parallel Arithmetic for Scalable AI Accelerators

Volume/Issue : 2026;03(07)

Page No : 1-14

The increasing adoption of high-dimensional data processing in image analysis, wireless communication, machine learning, biomedical signal processing, and real-time embedded systems has significantly increased the demand for efficient Singular Value Decomposition (SVD) hardware accelerators. SVD plays a critical role in applications such as feature extraction, noise reduction, image compression, adaptive filtering, MIMO communication systems, pattern recognition, and data analytics, where rapid and accurate matrix decomposition is essential for real-time decision-making. However, existing SVD architectures predominantly rely on sequential largest-element search mechanisms, conventional COordinate Rotation DIgital Computer (CORDIC) -based rotation processors, and limited memory organizations, resulting in increased search latency, memory access bottlenecks, higher computational complexity, reduced throughput, and slower convergence for large-scale matrices. To address these limitations, this work proposes a novel parallel SVD architecture incorporating an Iterative Vector Rotation Unit (IVRU), Parallel Scan Search Module (PSSM), Address and Data Synchronization Unit (ADSU), and Multi-Bank Memory (MBM). The PSSM accelerates dominant element identification through concurrent comparisons, while the MBM enables simultaneous read and write operations to eliminate memory contention. The ADSU ensures synchronized and conflict-free communication among processing modules, and the IVRU performs efficient iterative vector rotations for rapid matrix diagonalization. The integration of these modules significantly reduces computational latency, improves memory bandwidth utilization, enhances convergence speed, increases processing throughput, and provides a scalable hardware platform for high-performance real-time SVD computation in advanced signal processing and intelligent computing applications.

Keywords : Singular Value Decomposition (SVD), VLSI Architecture, Iterative Vector Rotation Unit (IVRU), Parallel Scan Search Module (PSSM), Multi-Bank Memory (MBM), High-Performance Computing, Real-Time Signal Processing, Hardware Accelerator.

Author : Gundala Praveena, Koppula Manasa

Title : Pipelined IVRU with Multi Bank Memory for Scalable SVD Acceleration Systems

Volume/Issue : 2026;03(07)

Page No : 15-30

Recent clinical and embedded sensing studies indicate that always-on respiratory audio monitoring including asthma wheeze detection and cough classification can consume more data in battery-powered wearable and Internet of Medical Things (IoMT) devices. Further, realtime respiratory sound classification is a critical requirement for wearable health monitors, smart inhalers, remote patient monitoring systems, and edge-based medical diagnostic sensors, where strict constraints on energy, memory, and inference latency prohibit conventional deployment. Traditional audio-based respiratory classifiers rely on fixed-precision Deep Neural Networks (DNNs) with high memory bandwidth and multiplier-intensive computation, making them unsuitable for long-term wearable operation. Existing BNN-based medical audio accelerators often employ static binarization and fixed temporal smoothing, leading to high output entropy, sensitivity to transient noise, and frequent false positives or missed pathological events. Furthermore, rigid hardware architectures restrict scalability and limit adaptation to new respiratory conditions or evolving clinical thresholds. To address these challenges, this work proposes a VLSI-optimized respiratory audio classification architecture based on an enhanced Binary Deep Neural Network. The design integrates a Scalable Hierarchical Binary Compute Array (SHBCA) for parallel and area-efficient binary computation, an Adaptive Entropy-Aware Binary Engine (AEABE) that dynamically regulates binarization thresholds to stabilize diagnostic confidence, and a Latency-Constrained Temporal Fusion Module (LCTFM) that exploits temporal correlations in respiratory sounds while maintaining bounded response time. Additionally, a Reconfigurable Respiratory Adaptation Fabric (RRAF) enables on-chip reconfiguration of disease-specific parameters without full model retraining. Collectively, the proposed architecture achieves a balanced trade-off between diagnostic accuracy, latency, and energy efficiency, making it well suited for edge-oriented IoMT respiratory monitoring systems.

Keywords : Respiratory Audio Classification, Very Large-Scale Integration (VLSI), Internet of Medical Things (IoMT), Edge Artificial Intelligence (Edge AI), Low-Power Hardware Accelerator

Author : Machika Navyasri, Tangerala Pradeep Kumar

Title : Scalable Binary Deep Neural Network Accelerator with Adaptive Temporal Analysis for Asthma and Cough Audio Classification

Volume/Issue : 2026;03(07)

Page No : 31-47

Sudden cardiac arrest (SCA) accounts for nearly 15–20% of all cardiac-related deaths worldwide, with survival rates dropping below 10% when early prediction and intervention are unavailable. Clinical studies show that heart rate variability (HRV)–based indicators can provide minutes-to-hours of early warning, yet real-time deployment remains constrained by computational and energy limitations of conventional platforms. The need for continuous, low-power, and real-time SCA prediction is critical in application scenarios such as wearable cardiac monitors, bedside intensive care units (ICUs), and remote telemedicine systems, where deterministic latency and long battery life are mandatory. Hardware-level acceleration is essential to enable always-on monitoring without reliance on cloud connectivity or high-power processors. Traditional hardware centric neural network solutions suffer from high inference latency, excessive power consumption, and limited scalability, while fixedprecision VLSI accelerators struggle with accuracy degradation under dynamic physiological variations and inefficient nonlinear activation implementations. These limitations hinder reliable early-warning deployment in safety-critical medical environments. To address these challenges, this work proposes a hardware-accelerated neural network architecture for early SCA prediction based on HRV, optimized at the VLSI level using four key innovations: the Adaptive Precision HRV Neural Core (AP-HNC) dynamically adjusts arithmetic bit-widths to balance accuracy and energy efficiency; the Parallel Systolic Cardiac Inference Engine (PS-CIE) employs a systolic MAC array to enable low-latency parallel neuron evaluation; the Scalable Modular Neuro-Control Fabric (SM-NCF) replaces monolithic control with hierarchical scheduling to support deeper and extensible neural models; and the Lightweight Hybrid Activation Predictor (LHAP) introduces LUT-assisted and piecewise-linear nonlinearities to significantly reduce area and power overhead. Together, these architectural enhancements deliver a scalable, energy-efficient, and real-time VLSI solution suitable for continuous cardiac monitoring and early SCA risk prediction in next-generation medical devices.

Keywords : Adaptive Precision HRV Neural Core (AP-HNC), Early Sudden Cardiac Arrest Prediction, Hardware Acceleration, Heart Rate Variability (HRV), Lightweight Hybrid Activation Predictor (LHAP), Parallel Systolic Cardiac Inference Engine (PS-CIE),

Author : Sanjay Nadem, Perala Prasad Rao

Title : Modular VLSI Neural Accelerator with Lightweight Activations for Sudden Cardiac Arrest Detection

Volume/Issue : 2026;03(07)

Page No : 48-63

In this present study the durability characteristics of Steel fiber reinforced Self compacting concrete (SFRSCC) is determined for M30 and M40 grade concrete mixes. Along with durability strength and sportivity is carried out and comparison is made with Plane self compacting concrete (SCC) by chemical resistance, Initial Surface Absorption Test (ISAT). In the present study, the rational mix design procedure for self-compacting concrete is used. SCC mixes contains large quantity of powder (material whose parcel size is 0.125 mm)to maintain the plastic yield of the properties of fresh concrete as per the general guidelines for design of SCC mixes given in the EFNARC (2005).The present project consists of two phases. In the first phase, SCC mixes for different grades are developed without steel fibers and with steel fibers. The mechanical properties like compressive strength of the different grades were studied. In the second phase, based on the experimental results, durability properties were studied with the using of specimens of size 100 mm × 100 mm × 100 mm. Durability studies like Acid attack factors, Acid-Durability factors, Sulphate attack factors, Sorptivity are studied for the Plain SCC and steel Fiber Reinforced SCC and a comparison is made.

Keywords :

Author : A PRASHANTH, E SRINIVAS

Title : STUDY ON STRENGTH AND DURABILITY PROPERITIES OF STEEL FIBRE REINFORCED SELF COMPACTING CONCRETE

Volume/Issue : 2026;03(07)

Page No : 64-72